Test operations involved in the manufacturing of electronic devices are commonly performed using commercial or custom Automated Test Equipment (ATE), often in conjunction with and under limited control of a test station host computer that provides management of manufacturing operations for one or more such ATE tools. The manufacturing test flow usually involves several test steps, some performed while electronic devices remain integrated on the surface of a single semiconductor wafer, and some performed on electronic devices after the wafer has been sawed into pieces consisting of singulated electronic devices. Sometimes, the singulated electronic devices are assembled into packages before the singulated electronic device testing is performed. Testing done on an electronic device contained on a wafer is referred to as “sort test”, and testing done on a singulated electronic device is referred to as “final test”, or sometimes “package test”.
The ATE (also referred to below as the “tester”) performs real-time control of the electronic test sequences and test conditions that are applied to the (electronic) devices-under-test (DUTs). This is enabled through a test program executing on one or more test site controller central processing units (CPUs), depending on system architecture, which control the pin electronics and power supplies that drive collections of test sites on the tester. Specification, for example, of the test content for the desired signal transition timing, voltage or current levels, pass/fail limit thresholds, vector/data sequences, test subroutine and pattern content, test flow branching, etc. is made through a combination of vector/pattern memory data files and compiled or linked test program files, created using custom tester-specific programming languages and a library of application programming interface (API) functions.
The test station host computer functions are generally limited to those facilitated by a factory automation (or workflow) interface to the ATE, typically including automated or manual material loading procedures, test program loading and test process initiation procedures, initiation of tester calibration procedures, test data buffering/archival, test and tester status indicators, tool utilization tracking and tool problem response procedures.
In a typical test system at final test, a test station unit handler, commonly referred to simply as a “handler”, serves to physically insert the singulated devices into sockets to provide electrical connection to the tester in preparation for testing. After testing has been performed, the handler removes the devices from the sockets and places them into physically separate containers, referred to as “bins”, under direction of the test program, and according to the test results of each individual device. Typically, the designated handler bin, derived from the pass/fail response of a DUT to the test sequence administered by the test program and determined by the test program is passed from the test program to a system controller on the tester and then to the handler through a handler interface without modification, except for any necessary data formatting that may be required for compliance with interface protocols.
The binning signals that are passed from the ATE to the handler instruct the handler to physically remove the DUT(s) that have completed testing from test sockets and to place them in the indicated bins. Typically, devices are sorted according to whether they passed or failed testing, and further, may in some cases be classified and sorted according to passing and failing sub-categories. The handler construction may in some cases limit the number of physical bins into which tested devices may be placed. A typical handler has on the order of eight bins available for this purpose, but the number of available bins may vary in different implementations.
Frequently the test procedures described above are applied to multiple devices at multiple test sites in parallel. At final test, the handler may insert multiple devices into test sockets to prepare them for parallel testing, the ATE (under test program control) may apply and evaluate test signals from all of these devices simultaneously, and may then, based on the test results, direct the handler through the ATE-handler interface to distribute each of the tested devices into the appropriate bin for that device. By testing groups of devices in parallel, in this fashion, the effective rate of processing devices through a final test manufacturing operation (e.g., the number of parts tested per hour) is increased over what it would be for a serial test operation.